Interpretation of the fourth generation SiC FET of unitedsic – the minimum RDS (on) is only 6m Ω

Recently, unitedsic announced the release of SiC devices with only 6m Ω on resistance (RDS (on)), which responded to the power supply designers’ pursuit of higher performance and higher efficiency SiC FET. At the same time, unitedsic also announced a series of SiC devices with different on resistance, so as to meet the diversified needs of customers. This is also a major update after unitedsic released its first fourth generation SiC FET in 2020.

Liu Luwei, vice president of sales in the Asia Pacific region of unitedsic, and Richard Chen, manager of FAE in the Asia Pacific region, received an exclusive interview with eeworld to interpret the characteristics of the full range of products of the fourth generation SiC FET of unitedsic. The new fourth generation SiC devices support 750V withstand voltage, which can better deal with the extreme conditions of unstable operation of high-voltage bus such as electric vehicles.

New 750V SiC FET series

Unitedsic has released 9 new device / package options with ratings of 6, 9, 11, 23, 33 and 44m Ω. All devices are packaged in to-247-4l, and 18, 23, 33, 44 and 60m Ω devices are also packaged in to-247-3l. This 750V extended series complements the existing 18 and 60m Ω devices. It provides designers with more device solutions and greater design flexibility. Therefore, it can achieve the best cost-effective trade-off while maintaining sufficient design margin and circuit robustness.

According to different on resistors and packaging forms, unitedsic has launched up to 13 product combinations.

Liu Luwei particularly stressed that the unitedsic high-performance FET is based on a unique cascode configuration, in which the high-performance SiC fast JFET is encapsulated with the cascode optimized Si MOSFET, so as to ensure that the gate drive is compatible with typical SiC MOSFET, Si IGBT and Si MOSFET drives. Therefore, the design change is small and can support fast and flexible product substitution. At the same time, the product yield, cost and reliability of this structure are further improved compared with traditional SiC MOSFET.

Richard also stressed that unitedsic’s broader SiC product portfolio can be optimized for customers’ energy consumption, cost or heat dissipation at different power levels, so as to improve design flexibility.

Unitedsic’s different RDS (on) subdivided product series can help customers optimize from the perspective of efficiency, cost and heat dissipation according to specific application scenarios

At the same time, in order to cooperate with customer selection, unitedsic also launched FET jet Calculator 2.0. The calculator integrates 26 typical topologies. For engineers who adopt SiC for the first time or are looking for the most suitable design for continuous improvement, this calculator can quickly and simply evaluate the performance of unitedsic FET in various power topologies, so as to avoid wasting time to create advanced simulation for unsuitable devices, so as to speed up research and development.

At the same time, the 6m Ω device also has the industry’s best 5 μ S short-circuit resistance, combined with the short-circuit protection function of the driver, so as to better protect the power devices.

The 6m Ω uj4sc075006k4s SiC FET has the best 5 μ S short circuit withstand capacity

Omnidirectional comparison of the fourth generation SiC FET

Compared with the current mainstream SiC FET in the industry, unitedsic has the best RDSON performance in both 650V and 750V products.

Richard interpreted the power consumption advantages of the fourth generation SiC of unitedsic with multiple groups of measured data. Richard said that although the fourth generation SiC is a 750V product, due to the realization of lower RDS (on), according to the actual test results, the conduction loss is greatly reduced compared with 650V products in the industry under the conditions of hard switch and soft switch.

If RDS (on) × According to index a, the 4th generation SiC FET can reach the lowest market value at high and low bare chip temperatures. RDS(on) × EOSs / QoSs, a FOM, is very important in hard switching applications. This value of the 4th generation SiC FET is half that of the closest competitor. RDS(on) × The FOS of coss (TR) is very important in soft switching applications. If the device with rated voltage of 750V of unitedsic is compared with the device with rated voltage of 650V of competitors, the value of the former is about 30% lower than the latter. For hard switching applications, the integrated diode of SiC FET is superior to the competitor’s Si MOSFET or SiC MOSFET technology in recovery speed and forward voltage drop.

Richard said that the third generation SiC products are optimized according to the soft and hard switches, while the excellent performance of the fourth generation products can meet the different needs of soft and hard switches at the same time.

“At present, the actual test results show that the RDS (on) characteristics of the fourth generation SiC of unitedsic are very close to the limit of material characteristics, realizing a real perfect switch,” Richard said.

Wide application space of the fourth generation SiC

With its excellent performance and differentiated combination, the fourth generation SiC can be widely used in fields requiring high performance and efficiency, such as electric vehicles and it infrastructure.

Firstly, in the field of electric vehicles, in order to reduce power loss and weight, the high-voltage bus is constantly improving. Ordinary cars are increasing from 400V to 500V or even higher. 750V SiC has enough design margin to meet the demand of higher voltage.

For the most important traction inverter applications, after the fourth generation SiC is adopted, compared with the efficiency of 750V IGBT system, the loss under full load is only 1 / 3 of the previous one, and in most light load or medium load situations, the loss is only 1 / 5 ~ 1 / 6 of IGBT.

Another mainstream application is for the circuit breaker. The traditional mechanical circuit breaker has a huge volume, complex system, and needs arc removal devices. However, the electronic circuit breaker realized by SiC MOSFET and JFET does not need arc removal circuits, so it can realize the perfect combination of small volume and high efficiency. Similarly, in the concept market such as wireless charging of electric vehicles, the fourth generation products of unitedsic can also achieve better performance.

In addition, for the part of IT infrastructure, because unitedsic products adopt a unique casecode structure, the driver is compatible with the driver of superjunction MOSFET. Customers can directly switch to SiC Based on the existing design to improve efficiency.

According to the actual test results of unitedsic for totem pole PFC and DC / DC LLC, SiC can achieve a very high efficiency level.

According to the actual test results of totem pole PFC, different RDS (on) can be selected according to different load applications, so as to achieve the best efficiency performance.

Compared with superjunction MOSFET, SiC is much better than traditional silicon devices under any load

The fourth generation SiC FET will further reduce the application threshold

Due to the limitation of silicon device characteristics, the progress of traditional MOSFET in improving efficiency is becoming slower and slower, while wide band gap semiconductor is very suitable for electric vehicles, it infrastructure and other applications in pursuit of efficiency because of its characteristics of high frequency, high temperature resistance and high voltage resistance.

With the release of the fourth generation SiC devices of unitedsic, its unique architecture, better RDS (on), higher withstand voltage and robustness, richer product portfolio and better cost performance continuously reduce the threshold of SiC application. At the same time, Liu Luwei also stressed that unitedsic is also actively making capital investment to optimize production capacity to meet customers’ mass production needs.

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Precautions for operation of stm8s103 hardware I2C

The SCL and SDA pins of stm8 are marked with T, i.e. pure open drain pin. When the pure open drain pin inputs 0, it is low, and the output 1 is in high resistance state instead of high level. Therefore, these two pins need to be added with pull resistance.

There is nothing wrong with setting SCL to output. SDA should be set as input when stm8 reads slave data as the host and output when stm8 writes data to the slave as the host. Here Pb_ CR1 should be set to 0 (open drain at output and floating at input). When SDA is used as output, its output rate is limited to O1 = slow (up to 2MHz), so PB_ It is not necessary to set the corresponding bit of CR2 to 1 (when output). In addition, when it is set to 1 (when SDA pin is input), will an interrupt be triggered? (preliminary thinking: I don’t think so. It’s I2C, not GPIO)

Register I2C_ Bit2 (named ack bit) in CR2 means that stm8 will automatically send ack (pull down SDA) after receiving data, and send no ack without setting this bit (keep it high regardless of SDA). When we read multiple bytes from an external sensor, the last byte must reply to no ack. At this time, when the penultimate byte is read, set the ACK bit to 0. However, this ack must be set before the next reading of the external sensor byte, otherwise it will not be sent automatically. It is recommended that after reading the last byte at a time, set the ACK bit that has just been cleared again.

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Maxim launches a new generation of Internet of things security chip based on chipdna PUF Technology

Security has become the primary task in the era of Internet of things, especially at the hardware level. Maxim hopes to bring security and low power consumption to Internet of things applications through its encryption processor.

As the world becomes more digital, the risks and fears of network security are also increasing. Only the security of software design can not meet the security requirements, but it is more and more necessary to consider security when designing hardware, even at the silicon level.

Maxim integrated (now officially part of ADI) has been working hard to achieve this goal. The company recently released a new low-power encryption controller, which uses physical non clonable function (PUF) technology to improve hardware security. This paper will analyze the characteristics of PUF technology and Maxim’s latest encryption unit.

About PUF

Before we get to know the products released by Maxim, let’s talk about PUF, which is one of the most important technologies in the field of hardware security.

PUFs can use challenge response to verify the equipment. Picture provided by sutar El Al

PUF is a hardware security technology, which uses the inherent changes of device characteristics to produce a non clonable and unique device response to a given input. The response of PUF is unique, random and repeatable. It can help the generation and “storage” of encryption key, making it very difficult to crack at the hardware or software level.

One of the main benefits of PUF is that it is a non-volatile technology, but it does not physically “store” keys.

On the contrary, PUF creates the key in a challenge response manner when needed, and then the key is erased almost instantaneously. As Maxim integrated said. “There is always a key, but you can never see it.” using PUF can realize powerful and highly secure encryption key storage at the hardware level, which is why Maxim incorporated it into the security platform chipdna PUF.

Maxim’s chipdna PUF

Maxim integrated has invested heavily in PUF technology, and its flagship product is chipdna PUF.

Chipdna works by taking advantage of the random changes naturally occurring in CMOS Design and the mismatch of analog characteristics. The following figure shows a simplified block diagram of PUF architecture. The example key size is 128 bits.

Simplified block diagram of chipdna PUF structure. Images provided by Maxim integrated

The figure above shows a 16 x 16 array of 256 analog PUF elements combined into 128 pairs. Due to process changes, each component will show random I / V characteristics, and then Maxim generates binary values through circuit level comparison of each pair of components. This process is repeated for all 128 pairs, resulting in a unique 128 bit key output.

Most importantly, as a hardware level security feature, chipdna PUF can be completely immune to all known invasive attacks (i.e. detection), so it can become a way to provide hardware level security.

Now that we have understood the general concepts of PUF and Maxim’s chipdna PUF, let’s finally have a deep understanding of the latest version.

Maxq1065 = low power and safety

Maxim’s latest security coprocessor maxq1065 is an ultra-low power encryption controller for the Internet of things.

In the application of Internet of things, low power consumption is one of its most important aspects. Maxq1065 achieves this. Its standby power consumption is less than 100na. Maxim says that compared with similar products, its power consumption can be reduced by 30 times.

The device aims to provide several security measures, including trust root, mutual authentication, data confidentiality and integrity, and secure startup.

Functional block diagram of maxq1065. Images provided by Maxim integrated

On this basis, maxq1065 uses chipdna PUF technology to prevent device level security attacks. Other hardware safety measures include.

A true random number generator (TRNG)
A TLS / dtls 1.2 handshake and recording layer
An 8 KB user data security memory

In the future, Maxim hopes to see the application of maxq1065 in Internet of things devices, such as supervisory control and data acquisition (SCADA), medical equipment, building and home automation, intelligent city and intelligent measurement. As the world becomes more connected, it will be crucial to continue to find low-power and high security processors.

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